1. Field of the Invention
The present invention relates to a method for programming and subsequently verifying a non-volatile memory.
More specifically, the present invention relates to a method for testing an electrically programmable non-volatile memory which includes a cell matrix and a state machine that governs the succession and timing of the memory programming phases through control signals.
2. Discussion of the Related Art
In very complex electronic devices such as, for example, non-volatile memories of the FLASH type, the testability aspect takes on considerable importance and should be evaluated during design.
As is known, a non-volatile memory circuit integrated on a semiconductor device includes a rather high number of memory cells structured essentially as a matrix. The cells are organized in word lines and bit lines. To program a certain cell the appropriate voltages must be brought to the respective word and bit lines which identify it.
In memories of this type, it is useful to verify correct operation of the matrix of the memory cells as well as the digital and/or analog control circuitry in the device.
To verify the absence of faults in the cell matrix it is useful to first carry out programming of the memory and to subsequently verify the correctness thereof.
Therefore, to perform the test, one conventionally uses the programming procedure and related circuitry provided for the purpose.
However, the programming is correct only if the related circuitry, i.e. the state machine, address decoders, the analog voltage generators, the control units, etc., are effectively and perfectly operating.
Additionally, it is not possible to change in a simple manner the duration of the programming and verification phases.
An object of the present invention is to provide a method for testing an electrically programmable non-volatile memory which allows greater testing speed and at the same time overcomes the shortcomings described above.